MEMS and NEMS technology continues to find new applications and employ multiple fabrication techniques. One known fabrication approach uses a high-temperature low pressure chemical vapor deposition (LPCVD) process to deposit polycrystalline silicon on top of a wafer with complementary metal-oxide-semiconductor (CMOS) circuitry. The polycrystalline silicon is then patterned to form a resonator.
In another known approach, a resonator is made through bulk micromachining on a silicon-on-insulator (SOI) wafer. The insulating layer acts as an etch stop for the deep reactive ion etch (DRIE) which defines the resonator shape in two dimensions (the plane of the wafer). The trenches are then refilled with silicon dioxide, and an epitaxial layer of silicon is grown over the device. This layer allows for circuitry to be later fabricated above the MEMS device. Next, holes are etched into the epitaxial layer to allow a vapor, such as a hydrofluoric (HF) acid etch in to selectively etch the silicon dioxide and release the resonator. Finally, the holes are filled using a vacuum deposition process resulting in a vacuum-sealed MEMS resonator.
Another known process is directed at producing a surface micromachined resonator similar to that above. However, this process uses polycrystalline SiGe instead of polycrystalline silicon. There are two methods: 1. Deposit the SiGe as a polycrystalline material which requires a lower temperature than that of polycrystalline silicon or 2. Deposit the SiGe at an even lower temperature which results in amorphous SiGe, and then use a laser to rapidly heat the surface which results in polycrystalline SiGe and does not affect any underlying circuitry.
Yet another process is similar to the previous except that a dome shape is achieved by depositing polycrystalline silicon over a sacrificial oxide at a temperature where the polycrystalline silicon is compressively stressed.
Existing methods include three release techniques: basic, backside, and surface micromachining.
For the basic release technique, the device is shaped on the front side of an SOI wafer. HF is then used to release the device by etching the insulator layer. Disadvantages include that the device's proximity to the substrate is defined by the insulator layer. This subjects the device to a higher risk of stiction during processing and operation.
For the backside release technique, SOI wafers have the device created on the front side. After all processing is completed, etch holes are patterned on the backside and the wafer is etched from the backside. The insulator layer behaves as an etch-stop. The insulator is then etched separately in an etch which is selective to just the insulator, which releases the structure. Disadvantages include a backside alignment which requires double-side polished wafers that is less accurate (front-to-back alignment) and which requires a larger dead-space around the device. This also requires a long backside etch and results in a weaker wafer.
For the surface micromachining technique, the devices are made above the plane of the wafer using processes such as chemical vapor deposition (CVD) to deposit the device material on top of a sacrificial material. The material is then patterned and the device is released using an etch which is selective to only the sacrificial material. The material used for this is not single-crystal, resulting in poorer behaviors including lower Q when used for a resonant device.
What is needed, therefore, are techniques for single-sided fabrication with enhanced compatibility of MEMS technology with standard CMOS technology and a process by which single-crystal MEMS/NEMS devices can be created alongside circuitry without the need for processing from the backside of the wafer.